The present invention relates generally to integrated circuit designs, and more particularly to electrostatic discharge (ESD) structures and circuits.
On-chip ESD protection mechanisms generally work in two ways. First, by dissipating the ESD current transient safely using a low-impedance discharging channel that prevents thermal damages in the structures of the integrated circuit. Secondly, by clamping any ESD induced voltage to a safe level to avoid dielectric degradation or rupture. Ideally the complete ESD protection solution should be realized on the integrated circuit (IC) creating an effective discharging channel from any pin to every other pin on the integrated circuit.
Devices that are used as ESD protection elements include diodes, bipolar transistors, MOSFETs and silicon-controlled rectifiers (SCRs). SCRs function as switches that can be configured to turn on and shunt voltage from the input and output pads of an integrated circuit to ground.
In ESD protection some integrated circuit elements may be more readily damaged by discharges occurring within automated equipment, while others may be more prone to damage from handling by personnel. This can occur from direct transfer of electrostatic charge from the human body or from a charged material to the electrostatic discharge sensitive (ESDS) element. When one walks across a floor, an electrostatic charge accumulates on the body. Simple contact of a finger to the leads of an ESDS device or assembly allows the body to discharge, possibly causing device damage. The model used to simulate this event is the Human Body Model (HBM).
The HBM testing model represents the discharge from the fingertip of a standing individual delivered to the device. It is modeled by a 100 pF capacitor discharged through a switching component and a 1.5 kOhm series resistor into the component. Typically, integrated circuit designers would like to see protection from the HBM testing to be greater than 2,000 volts.
An electrostatic discharge can also occur from a charged conductive object, such as a metallic tool or fixture. To test for this, designers use the Machine Model (MM). The machine model consists of a 200 pF capacitor discharged directly into a circuit without a series resistor. Typically, integrated circuit designers would like to see protection from the machine model to be greater than 200 volts.
Generally, to protect against ESD stress in CMOS ICs, an ESD protection structure consisting of several circuits is added to the ICs. A conventional ESD protection circuit has a two-stage structure for the device input pins. Generally the first stage is a robust device, such as an SCR, a field-oxide device, or a long-channel NMOS transistor, that functions as a primary protection device to discharge ESD current. The second stage is generally a gate-grounded short-channel NMOS transistor that functions as a secondary protection device to clamp the overstress voltage. Between the first stage and the second stage of the input ESD protection circuit, a resistor is added to limit the ESD current flowing through the second stage ESD clamp device. The value of this resistor is dependent on the turn-on voltage of the first stage ESD clamp device and the secondary breakdown current of the second stage ESD clamp device. Such resistance is designed large enough so the first stage ESD device can be triggered on to bypass ESD current before the second stage ESD clamp device is damaged by ESD. Such two-stage ESD protection design can provide high a ESD protection level for the digital input pins, but the series resistance and the junction capacitance in the ESD protection devices cause a resistive and capacitive effect that is not suitable for many analog circuits, especially for high frequency or current-mode applications.
As such, what is needed is an improved ESD protection structure.